diff options
| author | Stuart Brady <sdb@parisc-linux.org> | 2005-10-22 04:44:14 +0200 |
|---|---|---|
| committer | Kyle McMartin <kyle@parisc-linux.org> | 2005-10-22 04:44:14 +0200 |
| commit | 2464212f68136527f6364d63c23a529e1fd7d168 (patch) | |
| tree | 5a7a9b56570be465c87047a28d38aadf1357e698 /arch/parisc | |
| parent | [PARISC] Add ability for prctl to change unaligned trap behaviour (diff) | |
| download | linux-2464212f68136527f6364d63c23a529e1fd7d168.tar.xz linux-2464212f68136527f6364d63c23a529e1fd7d168.zip | |
[PARISC] Fix parisc_setup_cache_timing to choose a better flush threshold
update comment about CAFL_STRIDE
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Fixed a bug in parisc_setup_cache_timing() which caused it to calculate
a poor value for parisc_cache_flush_threshold.
Thanks to Joel Soete for spotting the bug.
Thanks to James Bottomley for pointing out the clean way to fix this.
Signed-off-by: Stuart Brady <sdb@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc')
| -rw-r--r-- | arch/parisc/kernel/cache.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index f46a07a79218..e15f09eaed12 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -27,6 +27,7 @@ #include <asm/page.h> #include <asm/pgalloc.h> #include <asm/processor.h> +#include <asm/sections.h> int split_tlb; int dcache_stride; @@ -207,6 +208,9 @@ parisc_cache_init(void) /* "New and Improved" version from Jim Hull * (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift)) + * The following CAFL_STRIDE is an optimized version, see + * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html + * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html */ #define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift)) dcache_stride = CAFL_STRIDE(cache_info.dc_conf); @@ -339,17 +343,15 @@ int parisc_cache_flush_threshold = FLUSH_THRESHOLD; void parisc_setup_cache_timing(void) { unsigned long rangetime, alltime; - extern char _text; /* start of kernel code, defined by linker */ - extern char _end; /* end of BSS, defined by linker */ unsigned long size; alltime = mfctl(16); flush_data_cache(); alltime = mfctl(16) - alltime; - size = (unsigned long)(&_end - _text); + size = (unsigned long)(_end - _text); rangetime = mfctl(16); - flush_kernel_dcache_range((unsigned long)&_text, size); + flush_kernel_dcache_range((unsigned long)_text, size); rangetime = mfctl(16) - rangetime; printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n", |