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| author | Daniel J Blueman <daniel@quora.org> | 2024-04-19 10:51:46 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2024-04-29 23:27:16 +0200 |
| commit | 455f9075f14484f358b3c1d6845b4a438de198a7 (patch) | |
| tree | fb947e378f6510de93f072b434e32f640845dd74 /arch/parisc | |
| parent | Linux 6.9-rc5 (diff) | |
| download | linux-455f9075f14484f358b3c1d6845b4a438de198a7.tar.xz linux-455f9075f14484f358b3c1d6845b4a438de198a7.zip | |
x86/tsc: Trust initial offset in architectural TSC-adjust MSRs
When the BIOS configures the architectural TSC-adjust MSRs on secondary
sockets to correct a constant inter-chassis offset, after Linux brings the
cores online, the TSC sync check later resets the core-local MSR to 0,
triggering HPET fallback and leading to performance loss.
Fix this by unconditionally using the initial adjust values read from the
MSRs. Trusting the initial offsets in this architectural mechanism is a
better approach than special-casing workarounds for specific platforms.
Signed-off-by: Daniel J Blueman <daniel@quora.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Steffen Persvold <sp@numascale.com>
Reviewed-by: James Cleverdon <james.cleverdon.external@eviden.com>
Reviewed-by: Dimitri Sivanich <sivanich@hpe.com>
Reviewed-by: Prarit Bhargava <prarit@redhat.com>
Link: https://lore.kernel.org/r/20240419085146.175665-1-daniel@quora.org
Diffstat (limited to 'arch/parisc')
0 files changed, 0 insertions, 0 deletions