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authorChristophe Leroy <christophe.leroy@c-s.fr>2016-05-17 09:02:54 +0200
committerScott Wood <oss@buserror.net>2016-07-09 09:02:48 +0200
commit4ad274502f66614eec3093aaa0cdeb4b70697ddf (patch)
tree0ca9e2c55cd25aba07b0218483e54aad0e35dfc2 /arch/powerpc/Kconfig
parentpowerpc/8xx: Don't use page table for linear memory space (diff)
downloadlinux-4ad274502f66614eec3093aaa0cdeb4b70697ddf.tar.xz
linux-4ad274502f66614eec3093aaa0cdeb4b70697ddf.zip
powerpc/8xx: Rework CONFIG_PIN_TLB handling
On recent kernels, with some debug options like for instance CONFIG_LOCKDEP, the BSS requires more than 8M memory, allthough the kernel code fits in the first 8M. Today, it is necessary to activate CONFIG_PIN_TLB to get more than 8M at startup, allthough pinning TLB is not necessary for that. We could have inconditionaly mapped 16 or 24M bytes at startup but some old hardware only have 8M and mapping non-existing RAM would be an issue due to speculative accesses. With the preceding patch however, the TLB entries are populated on demand. By setting up the TLB miss handler to handle up to 24M until the handler is patched for the entire memory space, it is possible to allow access up to more memory without mapping non-existing RAM. It is therefore not needed anymore to map memory data at all at startup. It will be handled by the TLB miss handler. One might still want to PIN the IMMR and the first 24M of RAM. It is now possible to do it in the C memory initialisation functions. In addition, we now know how much memory we have when we do it, so we are able to adapt the pining to the real amount of memory available. So boards with less than 24M can now also benefit from PIN_TLB. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
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