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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2017-07-12 12:08:51 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-08-15 14:55:53 +0200 |
| commit | a3059b0ca00bc3656ec47797e5816eeedaac3426 (patch) | |
| tree | 9115e3dc598c95a3750fd9d699b5a38f873ea782 /arch/powerpc/Kconfig | |
| parent | powerpc/32: Avoid risk of unrecoverable TLBmiss inside entry_32.S (diff) | |
| download | linux-a3059b0ca00bc3656ec47797e5816eeedaac3426.tar.xz linux-a3059b0ca00bc3656ec47797e5816eeedaac3426.zip | |
powerpc/8xx: Make pinning of ITLBs optional
As stated in a comment in head_8xx.S, today we "Always pin the first
8 MB ITLB to prevent ITLB misses while mucking around with SRR0/SRR1
in asm".
This issue has just been cleared by the preceding patch, therefore
we can make this pinning optional (on by default) and independent
of DATA pinning.
This patch also makes pinning of IMMR independent of pinning of DATA.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/Kconfig')
| -rw-r--r-- | arch/powerpc/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 2a290561e851..a4c575c95937 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -1178,10 +1178,20 @@ config PIN_TLB bool "Pinned Kernel TLBs (860 ONLY)" depends on ADVANCED_OPTIONS && PPC_8xx +config PIN_TLB_DATA + bool "Pinned TLB for DATA" + depends on PIN_TLB + default y + config PIN_TLB_IMMR bool "Pinned TLB for IMMR" depends on PIN_TLB default y + +config PIN_TLB_TEXT + bool "Pinned TLB for TEXT" + depends on PIN_TLB + default y endmenu if PPC64 |