diff options
| author | Adam Buchbinder <adam.buchbinder@gmail.com> | 2016-02-24 19:51:11 +0100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-03-01 09:27:20 +0100 |
| commit | 446957ba5127141ee007fc61509e24a9e60853d9 (patch) | |
| tree | 6e64ed20eaf8b4aa666eb3c77265e85f52594e50 /arch/powerpc/crypto | |
| parent | powerpc/ps3: gelic_udbg: use struct udphdr from <linux/udp.h> (diff) | |
| download | linux-446957ba5127141ee007fc61509e24a9e60853d9.tar.xz linux-446957ba5127141ee007fc61509e24a9e60853d9.zip | |
powerpc: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/crypto')
| -rw-r--r-- | arch/powerpc/crypto/aes-spe-core.S | 4 | ||||
| -rw-r--r-- | arch/powerpc/crypto/aes-spe-glue.c | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/crypto/aes-spe-core.S b/arch/powerpc/crypto/aes-spe-core.S index 5dc6bce90a77..bc6ff43a9889 100644 --- a/arch/powerpc/crypto/aes-spe-core.S +++ b/arch/powerpc/crypto/aes-spe-core.S @@ -61,7 +61,7 @@ * via bl/blr. It expects that caller has pre-xored input data with first * 4 words of encryption key into rD0-rD3. Pointer/counter registers must * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3 - * and rW0-rW3 and caller must execute a final xor on the ouput registers. + * and rW0-rW3 and caller must execute a final xor on the output registers. * All working registers rD0-rD3 & rW0-rW7 are overwritten during processing. * */ @@ -209,7 +209,7 @@ ppc_encrypt_block_loop: * via bl/blr. It expects that caller has pre-xored input data with first * 4 words of encryption key into rD0-rD3. Pointer/counter registers must * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3 - * and rW0-rW3 and caller must execute a final xor on the ouput registers. + * and rW0-rW3 and caller must execute a final xor on the output registers. * All working registers rD0-rD3 & rW0-rW7 are overwritten during processing. * */ diff --git a/arch/powerpc/crypto/aes-spe-glue.c b/arch/powerpc/crypto/aes-spe-glue.c index 93ee046d12cd..6d99ebf2ea15 100644 --- a/arch/powerpc/crypto/aes-spe-glue.c +++ b/arch/powerpc/crypto/aes-spe-glue.c @@ -32,7 +32,7 @@ * 16 byte block block or 25 cycles per byte. Thus 768 bytes of input data * will need an estimated maximum of 20,000 cycles. Headroom for cache misses * included. Even with the low end model clocked at 667 MHz this equals to a - * critical time window of less than 30us. The value has been choosen to + * critical time window of less than 30us. The value has been chosen to * process a 512 byte disk block in one or a large 1400 bytes IPsec network * packet in two runs. * |