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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-06-08 17:36:08 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-06-15 08:34:39 +0200 |
| commit | 9145effd626d155484f73db24ab3e142ecda31db (patch) | |
| tree | 0425c4849b69d9e4adc639a9e1969e95eb2d5901 /arch/powerpc/include/asm/barrier.h | |
| parent | powerpc/64: Drop reservation-clearing ldarx in context switch (diff) | |
| download | linux-9145effd626d155484f73db24ab3e142ecda31db.tar.xz linux-9145effd626d155484f73db24ab3e142ecda31db.zip | |
powerpc/64: Drop explicit hwsync in context switch
The sync (aka. hwsync, aka. heavyweight sync) in the context switch
code to prevent MMIO access being reordered from the point of view of
a single process if it gets migrated to a different CPU is not
required because there is an hwsync performed earlier in the context
switch path.
Comment this so it's clear enough if anything changes on the scheduler
or the powerpc sides. Remove the hwsync from _switch.
This improves context switch performance by 2-3% on POWER8.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/barrier.h')
| -rw-r--r-- | arch/powerpc/include/asm/barrier.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/barrier.h b/arch/powerpc/include/asm/barrier.h index c0deafc212b8..25d42bd3f114 100644 --- a/arch/powerpc/include/asm/barrier.h +++ b/arch/powerpc/include/asm/barrier.h @@ -74,6 +74,11 @@ do { \ ___p1; \ }) +/* + * This must resolve to hwsync on SMP for the context switch path. + * See _switch, and core scheduler context switch memory ordering + * comments. + */ #define smp_mb__before_spinlock() smp_mb() #include <asm-generic/barrier.h> |