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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2017-06-14 02:19:25 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2017-06-15 15:29:39 +0200
commit25642705b2359a705784bbbf1655c25a8f8efde2 (patch)
tree9bf28359bbc21c224f1eabdb3a6fce68e4eb271c /arch/powerpc/include/asm/bug.h
parentpowerpc/npu-dma: Remove spurious WARN_ON when a PCI device has no of_node (diff)
downloadlinux-25642705b2359a705784bbbf1655c25a8f8efde2.tar.xz
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powerpc/xive: Fix offset for store EOI MMIOs
Architecturally we should apply a 0x400 offset for these. Not doing it will break future HW implementations. The offset of 0 is supposed to remain for "triggers" though not all sources support both trigger and store EOI, and in P9 specifically, some sources will treat 0 as a store EOI. But future chips will not. So this makes us use the properly architected offset which should work always. Fixes: 243e25112d06 ("powerpc/xive: Native exploitation of the XIVE interrupt controller") Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/bug.h')
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