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authorZhao Chenhui <chenhui.zhao@freescale.com>2012-07-20 14:42:36 +0200
committerKumar Gala <galak@kernel.crashing.org>2012-09-12 21:57:08 +0200
commitd0832a75075b1119635e0f48549e378040cf5e67 (patch)
tree9d835dba5b7663517ea08cbde0b9b694614ba704 /arch/powerpc/include/asm/cacheflush.h
parentpowerpc/85xx: implement hardware timebase sync (diff)
downloadlinux-d0832a75075b1119635e0f48549e378040cf5e67.tar.xz
linux-d0832a75075b1119635e0f48549e378040cf5e67.zip
powerpc/85xx: add HOTPLUG_CPU support
Add support to disable and re-enable individual cores at runtime on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core. MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This patch uses the boot page from bootloader to boot core at runtime. It supports 32-bit and 36-bit physical address. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jin Qing <b24347@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/cacheflush.h')
-rw-r--r--arch/powerpc/include/asm/cacheflush.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/cacheflush.h b/arch/powerpc/include/asm/cacheflush.h
index ab9e402518e8..b843e35122e8 100644
--- a/arch/powerpc/include/asm/cacheflush.h
+++ b/arch/powerpc/include/asm/cacheflush.h
@@ -30,6 +30,8 @@ extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+extern void __flush_disable_L1(void);
+
extern void __flush_icache_range(unsigned long, unsigned long);
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{