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author | LEROY Christophe <christophe.leroy@c-s.fr> | 2015-01-19 17:04:44 +0100 |
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committer | Scott Wood <scottwood@freescale.com> | 2015-01-30 03:13:10 +0100 |
commit | cadbfd01468663e8b9f9518a58ef67398a20d06b (patch) | |
tree | 89c1cb6d6573baa71005f5eebfe21b6716542967 /arch/powerpc/include/asm/pte-8xx.h | |
parent | powerpc32: adds handling of _PAGE_RO (diff) | |
download | linux-cadbfd01468663e8b9f9518a58ef67398a20d06b.tar.xz linux-cadbfd01468663e8b9f9518a58ef67398a20d06b.zip |
powerpc/8xx: use _PAGE_RO instead of _PAGE_RW
On powerpc 8xx, in TLB entries, 0x400 bit is set to 1 for read-only pages
and is set to 0 for RW pages. So we should use _PAGE_RO instead of _PAGE_RW
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/pte-8xx.h')
-rw-r--r-- | arch/powerpc/include/asm/pte-8xx.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h index daa4616e61c4..eb6edb44f140 100644 --- a/arch/powerpc/include/asm/pte-8xx.h +++ b/arch/powerpc/include/asm/pte-8xx.h @@ -46,9 +46,9 @@ * require a TLB exception handler change. It is assumed unused bits * are always zero. */ -#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */ +#define _PAGE_RO 0x0400 /* lsb PP bits */ #define _PAGE_USER 0x0800 /* msb PP bits */ -/* set when neither _PAGE_USER nor _PAGE_RW are set */ +/* set when _PAGE_USER is unset and _PAGE_RO is set */ #define _PAGE_KNLRO 0x0200 #define _PMD_PRESENT 0x0001 @@ -62,9 +62,8 @@ #define PTE_ATOMIC_UPDATES 1 /* We need to add _PAGE_SHARED to kernel pages */ -#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_KNLRO) -#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_KNLRO) -#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE) +#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_RO | _PAGE_KNLRO) +#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_RO | _PAGE_KNLRO) #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_PTE_8xx_H */ |