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| author | Nicholas Piggin <npiggin@gmail.com> | 2022-01-22 11:56:39 +0100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2022-05-13 13:33:19 +0200 |
| commit | 861604614a94a7aabc111e4a18aaf5d56d270e8a (patch) | |
| tree | 70fc648e5f77be063c29cce39624d63d8beddcf2 /arch/powerpc/include/asm/reg.h | |
| parent | Linux 5.18-rc2 (diff) | |
| download | linux-861604614a94a7aabc111e4a18aaf5d56d270e8a.tar.xz linux-861604614a94a7aabc111e4a18aaf5d56d270e8a.zip | |
KVM: PPC: Book3S HV: HFSCR[PREFIX] does not exist
This facility is controlled by FSCR only. Reserved bits should not be
set in the HFSCR register (although it's likely harmless as this
position would not be re-used, and the L0 is forgiving here too).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220122105639.3477407-1-npiggin@gmail.com
Diffstat (limited to 'arch/powerpc/include/asm/reg.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 2835f6363228..1e14324c5190 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -417,7 +417,6 @@ #define FSCR_DSCR __MASK(FSCR_DSCR_LG) #define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */ #define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */ -#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG) #define HFSCR_MSGP __MASK(FSCR_MSGP_LG) #define HFSCR_TAR __MASK(FSCR_TAR_LG) #define HFSCR_EBB __MASK(FSCR_EBB_LG) |