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authorAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>2012-09-10 04:52:57 +0200
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-09-17 08:31:53 +0200
commit78f1dbde9fd020419313c2a0c3b602ea2427118f (patch)
tree9a5c34555b6fba6809ec33798e1aa53ce1ce0f53 /arch/powerpc/include/asm/tlbflush.h
parentpowerpc/mm: Update VSID allocation documentation (diff)
downloadlinux-78f1dbde9fd020419313c2a0c3b602ea2427118f.tar.xz
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powerpc/mm: Make some of the PGTABLE_RANGE dependency explicit
slice array size and slice mask size depend on PGTABLE_RANGE. Reviewed-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include/asm/tlbflush.h')
-rw-r--r--arch/powerpc/include/asm/tlbflush.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index fc02d1dee955..61a59271665b 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -103,9 +103,6 @@ DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
-extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, unsigned long pte, int huge);
-
#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
static inline void arch_enter_lazy_mmu_mode(void)