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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-11-28 07:17:03 +0100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-11-28 12:45:12 +0100 |
| commit | e58d1cf24309b3b58c7cff7ea1f873e498fdaa39 (patch) | |
| tree | eb3fa714a11b854b1771f87b660ea69d518c27f8 /arch/powerpc/include | |
| parent | powerpc/mm: update radix__ptep_set_access_flag to not do full mm tlb flush (diff) | |
| download | linux-e58d1cf24309b3b58c7cff7ea1f873e498fdaa39.tar.xz linux-e58d1cf24309b3b58c7cff7ea1f873e498fdaa39.zip | |
powerpc/mm: update radix__pte_update to not do full mm tlb flush
When we are updating a pte, we just need to flush the tlb mapping
that pte. Right now we do a full mm flush because we don't track page
size. Now that we have page size details in pte use that to do the
optimized flush
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/book3s/64/radix.h | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h index 36f636911ade..f4066cf31b3e 100644 --- a/arch/powerpc/include/asm/book3s/64/radix.h +++ b/arch/powerpc/include/asm/book3s/64/radix.h @@ -145,13 +145,7 @@ static inline unsigned long radix__pte_update(struct mm_struct *mm, * new value of pte */ new_pte = (old_pte | set) & ~clr; - - /* - * For now let's do heavy pid flush - * radix__flush_tlb_page_psize(mm, addr, mmu_virtual_psize); - */ - radix__flush_tlb_mm(mm); - + radix__flush_tlb_pte_p9_dd1(old_pte, mm, addr); __radix_pte_update(ptep, 0, new_pte); } else old_pte = __radix_pte_update(ptep, clr, set); |