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author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-04-29 15:25:58 +0200 |
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committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-01 10:33:00 +0200 |
commit | 2bfd65e45e877fb5704730244da67c748d28a1b8 (patch) | |
tree | 2e373df264786896da721a9f7fb105d67300fe3f /arch/powerpc/include | |
parent | powerpc/mm: Abstract early MMU init in preparation for radix (diff) | |
download | linux-2bfd65e45e877fb5704730244da67c748d28a1b8.tar.xz linux-2bfd65e45e877fb5704730244da67c748d28a1b8.zip |
powerpc/mm/radix: Add radix callbacks for early init routines
This adds routines for early setup for radix. We use device tree
property "ibm,processor-radix-AP-encodings" to find supported page
sizes. If we don't find the above we consider 64K and 4K as supported
page sizes.
We do map vmemap using 2M page size if we can. The linear mapping is
done such that we use required page size for that range. For example
memory of 3.5G is mapped such that we use 1G mapping till 3G range and
use 2M mapping for the rest.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/book3s/64/mmu.h | 17 | ||||
-rw-r--r-- | arch/powerpc/include/asm/book3s/64/radix.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 1 |
3 files changed, 19 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h index 37943f7af60f..94d52ff49bbe 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu.h +++ b/arch/powerpc/include/asm/book3s/64/mmu.h @@ -16,7 +16,10 @@ struct mmu_psize_def { int penc[MMU_PAGE_COUNT]; /* HPTE encoding */ unsigned int tlbiel; /* tlbiel supported for that page size */ unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ - unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ + union { + unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ + unsigned long ap; /* Ap encoding used by PowerISA 3.0 */ + }; }; extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; @@ -98,22 +101,34 @@ extern int mmu_vmemmap_psize; extern int mmu_io_psize; /* MMU initialization */ +extern void radix_init_native(void); extern void hash__early_init_mmu(void); +extern void radix__early_init_mmu(void); static inline void early_init_mmu(void) { + if (radix_enabled()) + return radix__early_init_mmu(); return hash__early_init_mmu(); } extern void hash__early_init_mmu_secondary(void); +extern void radix__early_init_mmu_secondary(void); static inline void early_init_mmu_secondary(void) { + if (radix_enabled()) + return radix__early_init_mmu_secondary(); return hash__early_init_mmu_secondary(); } extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base, phys_addr_t first_memblock_size); +extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base, + phys_addr_t first_memblock_size); static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base, phys_addr_t first_memblock_size) { + if (radix_enabled()) + return radix__setup_initial_memory_limit(first_memblock_base, + first_memblock_size); return hash__setup_initial_memory_limit(first_memblock_base, first_memblock_size); } diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h index db7e678e2bb6..a26259fcffd6 100644 --- a/arch/powerpc/include/asm/book3s/64/radix.h +++ b/arch/powerpc/include/asm/book3s/64/radix.h @@ -130,5 +130,7 @@ static inline int radix__pmd_trans_huge(pmd_t pmd) #endif +extern int radix__map_kernel_page(unsigned long ea, unsigned long pa, + pgprot_t flags, unsigned int psz); #endif /* __ASSEMBLY__ */ #endif diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 47082bcbf1e5..c1e82e968506 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -347,6 +347,7 @@ #define LPCR_LPES_SH 2 #define LPCR_RMI 0x00000002 /* real mode is cache inhibit */ #define LPCR_HDICE 0x00000001 /* Hyp Decr enable (HV,PR,EE) */ +#define LPCR_UPRT 0x00400000 /* Use Process Table (ISA 3) */ #ifndef SPRN_LPID #define SPRN_LPID 0x13F /* Logical Partition Identifier */ #endif |