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| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | 2017-10-09 16:12:40 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-12-20 10:53:11 +0100 |
| commit | 2d46d4877b1afd14059393a48bdb8ce27955174c (patch) | |
| tree | ab63b2fd93f73819eaaa4e2a59962f4e0b405f88 /arch/powerpc/include | |
| parent | powerpc/perf: Cleanup cache_sel bits comment (diff) | |
| download | linux-2d46d4877b1afd14059393a48bdb8ce27955174c.tar.xz linux-2d46d4877b1afd14059393a48bdb8ce27955174c.zip | |
powerpc/perf: Fix unit_sel/cache_sel checks
Raw event code has couple of fields "unit" and "cache" in it, to capture
the "unit" to monitor for a given pmcxsel and cache reload qualifier to
program in MMCR1.
isa207_get_constraint() refers "unit" field to update the MMCRC (L2/L3)
Event bus control fields with "cache" bits of the raw event code.
These are power8 specific and not supported by PowerISA v3.0 pmu. So wrap
the checks to be power8 specific. Also, "cache" bit field is referred to
update MMCR1[16:17] and this check can be power8 specific.
Fixes: 7ffd948fae4cd ('powerpc/perf: factor out power8 pmu functions')
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include')
0 files changed, 0 insertions, 0 deletions