diff options
| author | LEROY Christophe <christophe.leroy@c-s.fr> | 2014-09-19 10:36:09 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-08 01:10:43 +0100 |
| commit | 4094f28f90adab007eca9babf28f606a40a83032 (patch) | |
| tree | 4a9d47ec744360da9391ad705693ad8f5993c664 /arch/powerpc/kernel/head_8xx.S | |
| parent | powerpc/8xx: Better readibility of ERRATA CPU6 handling (diff) | |
| download | linux-4094f28f90adab007eca9babf28f606a40a83032.tar.xz linux-4094f28f90adab007eca9babf28f606a40a83032.zip | |
powerpc/8xx: set PTE bit 22 off TLBmiss
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/kernel/head_8xx.S')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 6e9124177f19..8d6e6830a675 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -447,14 +447,8 @@ DataStoreTLBMiss: and r11, r11, r10 rlwimi r10, r11, 0, _PAGE_PRESENT #endif - /* Honour kernel RO, User NA */ - /* 0x200 == Extended encoding, bit 22 */ - rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */ - /* r11 = (r10 & _PAGE_RW) >> 1 */ - rlwinm r11, r10, 32-1, 0x200 - or r10, r11, r10 - /* invert RW and 0x200 bits */ - xori r10, r10, _PAGE_RW | 0x200 + /* invert RW */ + xori r10, r10, _PAGE_RW /* The Linux PTE won't go exactly into the MMU TLB. * Software indicator bits 22 and 28 must be clear. |