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| author | Valentin Rothberg <valentinrothberg@gmail.com> | 2016-05-03 08:59:27 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-11 13:53:59 +0200 |
| commit | bb03efe2b7409d83a279ea1ef2317c26dbfb0c6c (patch) | |
| tree | 447140b6045782a700abd22e0b78a737c02f2cfa /arch/powerpc/kernel/mce_power.c | |
| parent | powerpc/mm/radix: Document software bits for radix (diff) | |
| download | linux-bb03efe2b7409d83a279ea1ef2317c26dbfb0c6c.tar.xz linux-bb03efe2b7409d83a279ea1ef2317c26dbfb0c6c.zip | |
powerpc/mm/radix: Fix CONFIG_PPC_MMU_STD_64 typo
It's CONFIG_PPC_STD_MMU_64 not ...
CONFIG_PPC_MMU_STD_64.
Fixes: 11ffc1cfa4c2 ("powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code")
Signed-off-by: Valentin Rothberg <valentinrothberg@gmail.com>
Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/mce_power.c')
| -rw-r--r-- | arch/powerpc/kernel/mce_power.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index bec70338672e..7353991c4ece 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -80,7 +80,7 @@ void __flush_tlb_power9(unsigned int action) /* flush SLBs and reload */ -#ifdef CONFIG_PPC_MMU_STD_64 +#ifdef CONFIG_PPC_STD_MMU_64 static void flush_and_reload_slb(void) { struct slb_shadow *slb; @@ -125,7 +125,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits) * reset the error bits whenever we handle them so that at the end * we can check whether we handled all of them or not. * */ -#ifdef CONFIG_PPC_MMU_STD_64 +#ifdef CONFIG_PPC_STD_MMU_64 if (dsisr & slb_error_bits) { flush_and_reload_slb(); /* reset error bits */ @@ -157,7 +157,7 @@ static long mce_handle_common_ierror(uint64_t srr1) switch (P7_SRR1_MC_IFETCH(srr1)) { case 0: break; -#ifdef CONFIG_PPC_MMU_STD_64 +#ifdef CONFIG_PPC_STD_MMU_64 case P7_SRR1_MC_IFETCH_SLB_PARITY: case P7_SRR1_MC_IFETCH_SLB_MULTIHIT: /* flush and reload SLBs for SLB errors. */ @@ -184,7 +184,7 @@ static long mce_handle_ierror_p7(uint64_t srr1) handled = mce_handle_common_ierror(srr1); -#ifdef CONFIG_PPC_MMU_STD_64 +#ifdef CONFIG_PPC_STD_MMU_64 if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) { flush_and_reload_slb(); handled = 1; @@ -332,7 +332,7 @@ static long mce_handle_ierror_p8(uint64_t srr1) handled = mce_handle_common_ierror(srr1); -#ifdef CONFIG_PPC_MMU_STD_64 +#ifdef CONFIG_PPC_STD_MMU_64 if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) { flush_and_reload_slb(); handled = 1; |