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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2016-02-09 17:08:21 +0100 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-03-12 00:20:11 +0100 |
| commit | 766d45cbeecc383b8ee230370b316d0b1e30d915 (patch) | |
| tree | 934a848219ee9f1aea3291bd0fafbf4166fc7dee /arch/powerpc/kernel/misc_32.S | |
| parent | powerpc/8xx: rewrite set_context() in C (diff) | |
| download | linux-766d45cbeecc383b8ee230370b316d0b1e30d915.tar.xz linux-766d45cbeecc383b8ee230370b316d0b1e30d915.zip | |
powerpc/8xx: rewrite flush_instruction_cache() in C
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/kernel/misc_32.S')
| -rw-r--r-- | arch/powerpc/kernel/misc_32.S | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index be8edd67f05b..7d1284f4d89e 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -296,12 +296,9 @@ _GLOBAL(real_writeb) * Flush instruction cache. * This is a no-op on the 601. */ +#ifndef CONFIG_PPC_8xx _GLOBAL(flush_instruction_cache) -#if defined(CONFIG_8xx) - isync - lis r5, IDC_INVALL@h - mtspr SPRN_IC_CST, r5 -#elif defined(CONFIG_4xx) +#if defined(CONFIG_4xx) #ifdef CONFIG_403GCX li r3, 512 mtctr r3 @@ -334,9 +331,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE) mfspr r3,SPRN_HID0 ori r3,r3,HID0_ICFI mtspr SPRN_HID0,r3 -#endif /* CONFIG_8xx/4xx */ +#endif /* CONFIG_4xx */ isync blr +#endif /* CONFIG_PPC_8xx */ /* * Write any modified data cache blocks out to memory |