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authorPaul Mackerras <paulus@samba.org>2009-02-24 01:33:56 +0100
committerPaul Mackerras <paulus@samba.org>2009-02-26 05:36:48 +0100
commit742bd95ba96e19b3f7196c3a0834ebc17c8ba006 (patch)
treeb55f7bc735577571b6bb71dd97ee73ce6b343f9d /arch/powerpc/kernel/perf_counter.c
parentperfcounters/powerpc: Make exclude_kernel bit work on Apple G5 processors (diff)
downloadlinux-742bd95ba96e19b3f7196c3a0834ebc17c8ba006.tar.xz
linux-742bd95ba96e19b3f7196c3a0834ebc17c8ba006.zip
perfcounters/powerpc: Add support for POWER5 processors
This adds the back-end for the PMU on the POWER5 processor. This knows how to use the fixed-function PMC5 and PMC6 (instructions completed and run cycles). Unlike POWER6, PMC5/6 obey the freeze conditions and can generate interrupts, so their use doesn't impose any extra restrictions. POWER5+ is different and is not supported by this patch. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/perf_counter.c')
-rw-r--r--arch/powerpc/kernel/perf_counter.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index 6e27913ec0d8..112332d07fc2 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -824,6 +824,7 @@ void hw_perf_counter_setup(int cpu)
}
extern struct power_pmu ppc970_pmu;
+extern struct power_pmu power5_pmu;
extern struct power_pmu power6_pmu;
static int init_perf_counters(void)
@@ -843,6 +844,9 @@ static int init_perf_counters(void)
case PV_970MP:
ppmu = &ppc970_pmu;
break;
+ case PV_POWER5:
+ ppmu = &power5_pmu;
+ break;
case 0x3e:
ppmu = &power6_pmu;
break;