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| author | Becky Bruce <becky.bruce@freescale.com> | 2007-08-02 22:37:15 +0200 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2007-08-17 20:22:28 +0200 |
| commit | 86d7a9a9c4775f864e6bc5f5da66ef9ea3715734 (patch) | |
| tree | 43e7a2d1b54c10e28d8607d15c454ea6556f764c /arch/powerpc/kernel/traps.c | |
| parent | [POWERPC] Fix interrupt routing and setup of ULI M1575 on FSL boards (diff) | |
| download | linux-86d7a9a9c4775f864e6bc5f5da66ef9ea3715734.tar.xz linux-86d7a9a9c4775f864e6bc5f5da66ef9ea3715734.zip | |
[POWERPC] Fix FSL BookE machine check reporting
Reserved MCSR bits on FSL BookE parts may have spurious values
when mcheck occurs. Mask these off when printing the MCSR to
avoid confusion. Also, get rid of the MCSR_GL_CI bit defined
for e500 - this bit doesn't actually have any meaning.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/traps.c')
| -rw-r--r-- | arch/powerpc/kernel/traps.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c index 2bb1cb911783..d8502e377518 100644 --- a/arch/powerpc/kernel/traps.c +++ b/arch/powerpc/kernel/traps.c @@ -299,7 +299,7 @@ static inline int check_io_access(struct pt_regs *regs) #ifndef CONFIG_FSL_BOOKE #define get_mc_reason(regs) ((regs)->dsisr) #else -#define get_mc_reason(regs) (mfspr(SPRN_MCSR)) +#define get_mc_reason(regs) (mfspr(SPRN_MCSR) & MCSR_MASK) #endif #define REASON_FP ESR_FP #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) @@ -414,8 +414,6 @@ void machine_check_exception(struct pt_regs *regs) printk("Data Cache Push Parity Error\n"); if (reason & MCSR_DCPERR) printk("Data Cache Parity Error\n"); - if (reason & MCSR_GL_CI) - printk("Guarded Load or Cache-Inhibited stwcx.\n"); if (reason & MCSR_BUS_IAERR) printk("Bus - Instruction Address Error\n"); if (reason & MCSR_BUS_RAERR) |