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authorAlastair D'Silva <alastair@d-silva.org>2019-11-04 03:32:54 +0100
committerMichael Ellerman <mpe@ellerman.id.au>2019-11-07 12:48:34 +0100
commitf9ec11165301982585e5e5f606739b5bae5331f3 (patch)
treed5fef584c8cf8e702fd08fc1c35c0cc3eeedad65 /arch/powerpc/kernel/vdso64/cacheflush.S
parentpowerpc: Allow flush_icache_range to work across ranges >4GB (diff)
downloadlinux-f9ec11165301982585e5e5f606739b5bae5331f3.tar.xz
linux-f9ec11165301982585e5e5f606739b5bae5331f3.zip
powerpc: Allow 64bit VDSO __kernel_sync_dicache to work across ranges >4GB
When calling __kernel_sync_dicache with a size >4GB, we were masking off the upper 32 bits, so we would incorrectly flush a range smaller than intended. This patch replaces the 32 bit shifts with 64 bit ones, so that the full size is accounted for. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Cc: stable@vger.kernel.org Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20191104023305.9581-3-alastair@au1.ibm.com
Diffstat (limited to 'arch/powerpc/kernel/vdso64/cacheflush.S')
-rw-r--r--arch/powerpc/kernel/vdso64/cacheflush.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/vdso64/cacheflush.S b/arch/powerpc/kernel/vdso64/cacheflush.S
index 3f92561a64c4..526f5ba2593e 100644
--- a/arch/powerpc/kernel/vdso64/cacheflush.S
+++ b/arch/powerpc/kernel/vdso64/cacheflush.S
@@ -35,7 +35,7 @@ V_FUNCTION_BEGIN(__kernel_sync_dicache)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8
@@ -52,7 +52,7 @@ V_FUNCTION_BEGIN(__kernel_sync_dicache)
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
crclr cr0*4+so
beqlr /* nothing to do? */
mtctr r8