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authorNicholas Piggin <npiggin@gmail.com>2017-04-18 21:12:16 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2017-04-26 03:40:21 +0200
commit8bf8f2e8c786f37991bd27332c75edcc524d2232 (patch)
tree8892a475d2b21038cdfd8ff2fdd727c1853ff0ea /arch/powerpc/kvm/book3s_32_mmu.c
parentpowerpc: Fixup LPCR:PECE and HEIC setting on POWER9 (diff)
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powerpc/64s: Revert setting of LPCR[LPES] on POWER9
The XIVE enablement patches included a change to set the LPES (Logical Partitioning Environment Selector) bit (bit # 3) in LPCR (Logical Partitioning Control Register) on POWER9 hosts. This bit sets external interrupts to guest delivery mode, which uses SRR0/1. The host's EE interrupt handler is written to expect HSRR0/1 (for earlier CPUs). This should be fine because XIVE is configured not to deliver EEs to the host (Hypervisor Virtulization Interrupt is used instead) so the EE handler should never be executed. However a bug in interrupt controller code, hardware, or odd configuration of a simulator could result in the host getting an EE incorrectly. Keeping the EE delivery mode matching the host EE handler prevents strange crashes due to using the wrong exception registers. KVM will configure the LPCR to set LPES prior to running a guest so that EEs are delivered to the guest using SRR0/1. Fixes: 08a1e650cc ("powerpc: Fixup LPCR:PECE and HEIC setting on POWER9") Signed-off-by: Nicholas Piggin <npiggin@gmail.com> [mpe: Massage change log to avoid referring to LPES0 which is now renamed LPES] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kvm/book3s_32_mmu.c')
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