diff options
| author | James Yang <James.Yang@freescale.com> | 2013-07-04 23:18:44 +0200 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-08-14 06:59:57 +0200 |
| commit | cc7059b5ea730edde256deb94a42f8e9e732d9b8 (patch) | |
| tree | 227c68582067ee0700b8befa841e34f90b8b4ffa /arch/powerpc/math-emu/math.c | |
| parent | powerpc: Remove the empty giveup_fpu() function on 32bit kernel (diff) | |
| download | linux-cc7059b5ea730edde256deb94a42f8e9e732d9b8.tar.xz linux-cc7059b5ea730edde256deb94a42f8e9e732d9b8.zip | |
powerpc/math-emu: Fix load/store indexed emulation
Load/store indexed instructions where the index register RA=R0, such
as "lfdx f1,0,r3", are not illegal.
Load/store indexed with update instructions where the index register
RA=R0, such as "lfdux f1,0,r3", are invalid, and, to be consistent
with existing math-emu behavior for other invalid instruction forms,
will signal as illegal.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/math-emu/math.c')
| -rw-r--r-- | arch/powerpc/math-emu/math.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/arch/powerpc/math-emu/math.c b/arch/powerpc/math-emu/math.c index bc901623d8df..ab151f040502 100644 --- a/arch/powerpc/math-emu/math.c +++ b/arch/powerpc/math-emu/math.c @@ -380,21 +380,16 @@ do_mathemu(struct pt_regs *regs) case XE: idx = (insn >> 16) & 0x1f; op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); - if (!idx) { - if (((insn >> 1) & 0x3ff) == STFIWX) - op1 = (void *)(regs->gpr[(insn >> 11) & 0x1f]); - else - goto illegal; - } else { - op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]); - } - + op1 = (void *)((idx ? regs->gpr[idx] : 0) + + regs->gpr[(insn >> 11) & 0x1f]); break; case XEU: idx = (insn >> 16) & 0x1f; + if (!idx) + goto illegal; op0 = (void *)¤t->thread.TS_FPR((insn >> 21) & 0x1f); - op1 = (void *)((idx ? regs->gpr[idx] : 0) + op1 = (void *)(regs->gpr[idx] + regs->gpr[(insn >> 11) & 0x1f]); break; |