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authorChristophe Leroy <christophe.leroy@c-s.fr>2019-02-21 20:08:51 +0100
committerMichael Ellerman <mpe@ellerman.id.au>2019-02-23 11:04:32 +0100
commitd5f17ee96447736a84bc44ffc4b0dddb1b519222 (patch)
tree6cd30783636f3e54bdec42c13b3e95af096762c6 /arch/powerpc/mm/mmu_decl.h
parentpowerpc/kconfig: make _etext and data areas alignment configurable on Book3s 32 (diff)
downloadlinux-d5f17ee96447736a84bc44ffc4b0dddb1b519222.tar.xz
linux-d5f17ee96447736a84bc44ffc4b0dddb1b519222.zip
powerpc/8xx: don't disable large TLBs with CONFIG_STRICT_KERNEL_RWX
This patch implements handling of STRICT_KERNEL_RWX with large TLBs directly in the TLB miss handlers. To do so, etext and sinittext are aligned on 512kB boundaries and the miss handlers use 512kB pages instead of 8Mb pages for addresses close to the boundaries. It sets RO PP flags for addresses under sinittext. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/mmu_decl.h')
-rw-r--r--arch/powerpc/mm/mmu_decl.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 98fc94affc29..74ff61dabcb1 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -166,7 +166,7 @@ static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
#endif
-#if defined(CONFIG_PPC_BOOK3S_32)
+#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
void mmu_mark_initmem_nx(void);
void mmu_mark_rodata_ro(void);
#else