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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-04-29 15:25:35 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-05-01 10:32:29 +0200 |
| commit | 96270b1fc25d527b015c73533119f6c85df2e0ff (patch) | |
| tree | 63e49ef4b22593a05986a65221018aef907298f0 /arch/powerpc/mm/pgtable_64.c | |
| parent | powerpc/mm: Replace _PAGE_USER with _PAGE_PRIVILEGED (diff) | |
| download | linux-96270b1fc25d527b015c73533119f6c85df2e0ff.tar.xz linux-96270b1fc25d527b015c73533119f6c85df2e0ff.zip | |
powerpc/mm: Remove RPN_SHIFT and RPN_SIZE
PTE_RPN_SHIFT is actually page size dependent. Even though PowerISA 3.0
expects only the lower 12 bits to be zero, we will always find the pages
to be PAGE_SHIFT aligned. In case of hash config, this also allows us to
use the additional 3 bits to track pte specific information. We need
to make sure we use these bits only for hash specific pte flags.
For both 4K and 64K config, pte now can hold 57 bits address.
Inorder to keep things simpler, drop PTE_RPN_SHIFT and PTE_RPN_SIZE and
specify the 57 bit detail explicitly.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/pgtable_64.c')
| -rw-r--r-- | arch/powerpc/mm/pgtable_64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index 603db71ff21d..9e0553eafcb7 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -757,7 +757,7 @@ pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot) { unsigned long pmdv; - pmdv = (pfn << PTE_RPN_SHIFT) & PTE_RPN_MASK; + pmdv = (pfn << PAGE_SHIFT) & PTE_RPN_MASK; return pmd_set_protbits(__pmd(pmdv), pgprot); } |