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| author | Dave Airlie <airlied@redhat.com> | 2011-03-16 02:34:41 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-03-16 02:34:41 +0100 |
| commit | 38f1cff0863809587b5fd10ecd0c24c8b543a48c (patch) | |
| tree | 7cf6eb88cdc938c3683209d38311e711a1119400 /arch/powerpc/mm/tlb_hash64.c | |
| parent | drm: Retry i2c transfer of EDID block after failure (diff) | |
| parent | drm/radeon: fix problem with changing active VRAM size. (v2) (diff) | |
| download | linux-38f1cff0863809587b5fd10ecd0c24c8b543a48c.tar.xz linux-38f1cff0863809587b5fd10ecd0c24c8b543a48c.zip | |
Merge commit '5359533801e3dd3abca5b7d3d985b0b33fd9fe8b' into drm-core-next
This commit changed an internal radeon structure, that meant a new driver
in -next had to be fixed up, merge in the commit and fix up the driver.
Also fixes a trivial nouveau merge.
Conflicts:
drivers/gpu/drm/nouveau/nouveau_mem.c
Diffstat (limited to 'arch/powerpc/mm/tlb_hash64.c')
| -rw-r--r-- | arch/powerpc/mm/tlb_hash64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c index 1ec06576f619..c14d09f614f3 100644 --- a/arch/powerpc/mm/tlb_hash64.c +++ b/arch/powerpc/mm/tlb_hash64.c @@ -38,13 +38,11 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch); * neesd to be flushed. This function will either perform the flush * immediately or will batch it up if the current CPU has an active * batch on it. - * - * Must be called from within some kind of spinlock/non-preempt region... */ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, pte_t *ptep, unsigned long pte, int huge) { - struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch); + struct ppc64_tlb_batch *batch = &get_cpu_var(ppc64_tlb_batch); unsigned long vsid, vaddr; unsigned int psize; int ssize; @@ -99,6 +97,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, */ if (!batch->active) { flush_hash_page(vaddr, rpte, psize, ssize, 0); + put_cpu_var(ppc64_tlb_batch); return; } @@ -127,6 +126,7 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, batch->index = ++i; if (i >= PPC64_TLB_BATCH_NR) __flush_tlb_pending(batch); + put_cpu_var(ppc64_tlb_batch); } /* |