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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-01-23 18:21:09 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@ti.com> | 2011-03-10 21:23:13 +0100 |
| commit | 9062511097683b4422f023d181b4a8b2db1a7a72 (patch) | |
| tree | 9e46fb8c0491a26bb25464d90b6cd4caf92edf5b /arch/powerpc/mm/tlb_hash64.c | |
| parent | OMAP3: PM: Remove un-necessary cp15 registers form low power cpu context (diff) | |
| download | linux-9062511097683b4422f023d181b4a8b2db1a7a72.tar.xz linux-9062511097683b4422f023d181b4a8b2db1a7a72.zip | |
OMAP3: PM: Clear the SCTLR C bit in asm code to prevent data cache allocation
On the newer ARM processors like CortexA8, CortexA9, the caches can be
speculatively loaded while they are getting flushed.
Clear the SCTLR C bit to prevent further data cache allocation as
part of cache clean routine
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch/powerpc/mm/tlb_hash64.c')
0 files changed, 0 insertions, 0 deletions