diff options
| author | Madhavan Srinivasan <maddy@linux.vnet.ibm.com> | 2017-10-09 16:12:39 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-12-20 10:53:11 +0100 |
| commit | 8c31459d6138b07537346d976e7c30c760a1de01 (patch) | |
| tree | c02da7b0920cece55b6706e1b72807fa2d0bb939 /arch/powerpc/perf/power9-pmu.c | |
| parent | powerpc/perf: Update perf_regs structure to include SIER (diff) | |
| download | linux-8c31459d6138b07537346d976e7c30c760a1de01.tar.xz linux-8c31459d6138b07537346d976e7c30c760a1de01.zip | |
powerpc/perf: Cleanup cache_sel bits comment
Update the raw event code comment in power9-pmu.c with respect to
"cache" bits, since power9 MMCRC does not support these.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/perf/power9-pmu.c')
| -rw-r--r-- | arch/powerpc/perf/power9-pmu.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c index e012b1030a5b..a5f8c563001b 100644 --- a/arch/powerpc/perf/power9-pmu.c +++ b/arch/powerpc/perf/power9-pmu.c @@ -63,16 +63,8 @@ * MMCRA[9:11] = thresh_cmp[0:2] * MMCRA[12:18] = thresh_cmp[3:9] * - * if unit == 6 or unit == 7 - * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) - * else if unit == 8 or unit == 9: - * if cache_sel[0] == 0: # L3 bank - * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) - * else if cache_sel[0] == 1: - * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) - * else if cache_sel[1]: # L1 event - * MMCR1[16] = cache_sel[2] - * MMCR1[17] = cache_sel[3] + * MMCR1[16] = cache_sel[2] + * MMCR1[17] = cache_sel[3] * * if mark: * MMCRA[63] = 1 (SAMPLE_ENABLE) |