diff options
| author | chenhui zhao <chenhui.zhao@freescale.com> | 2015-11-20 10:13:58 +0100 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-03-05 06:44:51 +0100 |
| commit | e7affb1dba0e9068aeb3978e858f39753e0dc20a (patch) | |
| tree | acc3b13685888fd5ad9ba6a67b0b6235447eba7f /arch/powerpc/platforms/85xx/smp.c | |
| parent | powerpc/mm: any thread in one core can be the first to setup TLB1 (diff) | |
| download | linux-e7affb1dba0e9068aeb3978e858f39753e0dc20a.tar.xz linux-e7affb1dba0e9068aeb3978e858f39753e0dc20a.zip | |
powerpc/cache: add cache flush operation for various e500
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches inside the current cpu.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@feescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/platforms/85xx/smp.c')
| -rw-r--r-- | arch/powerpc/platforms/85xx/smp.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 6b107cea1c08..4a7841616c7f 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -139,7 +139,8 @@ static void smp_85xx_mach_cpu_die(void) mtspr(SPRN_TCR, 0); - __flush_disable_L1(); + cur_cpu_spec->cpu_down_flush(); + tmp = (mfspr(SPRN_HID0) & ~(HID0_DOZE|HID0_SLEEP)) | HID0_NAP; mtspr(SPRN_HID0, tmp); isync(); @@ -359,7 +360,7 @@ void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary) local_irq_disable(); if (secondary) { - __flush_disable_L1(); + cur_cpu_spec->cpu_down_flush(); atomic_inc(&kexec_down_cpus); /* loop forever */ while (1); |