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authorYueHaibing <yuehaibing@huawei.com>2020-03-03 09:56:04 +0100
committerMichael Ellerman <mpe@ellerman.id.au>2020-03-17 13:40:36 +0100
commita4037d1f1fc4e92b69d7196d4568c33078d465ea (patch)
tree469823056f7afda85d48ef94788e0ce9649cb933 /arch/powerpc/platforms
parentpowerpc/pmac/smp: Avoid unused-variable warnings (diff)
downloadlinux-a4037d1f1fc4e92b69d7196d4568c33078d465ea.tar.xz
linux-a4037d1f1fc4e92b69d7196d4568c33078d465ea.zip
powerpc/pmac/smp: Drop unnecessary volatile qualifier
core99_l2_cache/core99_l3_cache do not need to be marked as volatile, remove it. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200303085604.24952-1-yuehaibing@huawei.com
Diffstat (limited to 'arch/powerpc/platforms')
-rw-r--r--arch/powerpc/platforms/powermac/smp.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index 4a2a1b2529b3..d2900689d642 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -664,8 +664,8 @@ static void core99_init_caches(int cpu)
{
#ifndef CONFIG_PPC64
/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
- volatile static long int core99_l2_cache;
- volatile static long int core99_l3_cache;
+ static long int core99_l2_cache;
+ static long int core99_l3_cache;
if (!cpu_has_feature(CPU_FTR_L2CR))
return;