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authorLinus Torvalds <torvalds@linux-foundation.org>2010-04-30 02:16:36 +0200
committerLinus Torvalds <torvalds@linux-foundation.org>2010-04-30 02:16:36 +0200
commit553cbf0a8f19c669bed82028988aa977558ef551 (patch)
treec0aecc102d1d3bf26f56dc69775d1657a456e2d4 /arch/powerpc/sysdev/cpm1.c
parentMerge branch 'bugfixes' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6 (diff)
parentpowerpc/ps3: Update ps3_defconfig (diff)
downloadlinux-553cbf0a8f19c669bed82028988aa977558ef551.tar.xz
linux-553cbf0a8f19c669bed82028988aa977558ef551.zip
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc/ps3: Update ps3_defconfig powerpc/ps3: Update platform maintainer powerpc/pseries: Flush lazy kernel mappings after unplug operations powerpc/numa: Add form 1 NUMA affinity powerpc/fsl-booke: Fix CONFIG_RELOCATABLE support on FSL Book-E ppc32 powerpc: 2.6.34 update of defconfigs for embedded 6xx/7xxx, 8xx, 8xxx powerpc/mpc8xxx defconfigs - turn off SYSFS_DEPRECATED powerpc/83xx: configure SIL SATA driver in 83xx-wide defconfig powerpc/83xx: enable EPOLL syscall in defconfig powerpc/83xx: add RTC drivers in 83xx defconfig powerpc/fsl-cpm: Configure clock correctly for SCC powerpc/fsl_booke: Correct test for MMU_FTR_BIG_PHYS powerpc/85xx/86xx: Fix build w/ CONFIG_PCI=n
Diffstat (limited to 'arch/powerpc/sysdev/cpm1.c')
-rw-r--r--arch/powerpc/sysdev/cpm1.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 4dae3698bf24..8d103ca6d6ab 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -486,9 +486,6 @@ int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
return -EINVAL;
}
- if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
- shift += 3;
-
for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
if (clk_map[i][0] == target && clk_map[i][1] == clock) {
bits = clk_map[i][2];
@@ -503,6 +500,17 @@ int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
bits <<= shift;
mask <<= shift;
+
+ if (reg == &mpc8xx_immr->im_cpm.cp_sicr) {
+ if (mode == CPM_CLK_RTX) {
+ bits |= bits << 3;
+ mask |= mask << 3;
+ } else if (mode == CPM_CLK_RX) {
+ bits <<= 3;
+ mask <<= 3;
+ }
+ }
+
out_be32(reg, (in_be32(reg) & ~mask) | bits);
return 0;