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authorKumar Gala <galak@kernel.crashing.org>2008-04-19 17:41:43 +0200
committerKumar Gala <galak@kernel.crashing.org>2008-04-21 17:19:09 +0200
commit546be91915a17e4faa9df91caa3ace0c92efa3ab (patch)
treef82c9c3fb841825f39b71808f6b58cc9e239668e /arch/ppc/syslib
parent[POWERPC] Fix compile breakage for 64-bit UP configs (diff)
downloadlinux-546be91915a17e4faa9df91caa3ace0c92efa3ab.tar.xz
linux-546be91915a17e4faa9df91caa3ace0c92efa3ab.zip
[PPC] Remove mpc8272 ads board from arch/ppc
We have a board port in arch/powerpc so we dont need this one anymore. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/ppc/syslib')
-rw-r--r--arch/ppc/syslib/m8260_setup.c6
-rw-r--r--arch/ppc/syslib/m82xx_pci.c38
2 files changed, 0 insertions, 44 deletions
diff --git a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
index 46588fa94381..b40583724de3 100644
--- a/arch/ppc/syslib/m8260_setup.c
+++ b/arch/ppc/syslib/m8260_setup.c
@@ -175,12 +175,6 @@ m8260_init_IRQ(void)
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
-
-#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
- /* Initialize stuff for the 82xx CPLD IC and install demux */
- pq2pci_init_irq();
-#endif
-
}
/*
diff --git a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
index fe860d52e2e4..657a1c25a2ab 100644
--- a/arch/ppc/syslib/m82xx_pci.c
+++ b/arch/ppc/syslib/m82xx_pci.c
@@ -150,14 +150,6 @@ pq2pci_init_irq(void)
{
int irq;
volatile cpm2_map_t *immap = cpm2_immr;
-#if defined CONFIG_ADS8272
- /* configure chip select for PCI interrupt controller */
- immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
- immap->im_memctl.memc_or3 = 0xffff8010;
-#elif defined CONFIG_PQ2FADS
- immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
- immap->im_memctl.memc_or8 = 0xffff8010;
-#endif
for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
irq_desc[irq].chip = &pq2pci_ic;
@@ -222,26 +214,6 @@ pq2ads_setup_pci(struct pci_controller *hose)
immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
#endif
-#if defined CONFIG_ADS8272
- immap->im_siu_conf.siu_82xx.sc_siumcr =
- (immap->im_siu_conf.siu_82xx.sc_siumcr &
- ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
- SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
- SIUMCR_LBPC11 | SIUMCR_APPC11 |
- SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
- SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
- SIUMCR_APPC10 | SIUMCR_CS10PC00 |
- SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
-
-#elif defined CONFIG_PQ2FADS
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
- * and local bus for PCI (SIUMCR [LBPC]).
- */
- immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.siu_82xx.sc_siumcr &
- ~(SIUMCR_L2CPC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
- SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10);
-#endif
/* Enable PCI */
immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
@@ -284,12 +256,6 @@ pq2ads_setup_pci(struct pci_controller *hose)
immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
-#if defined CONFIG_ADS8272
- /* PCI int highest prio */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
-#elif defined CONFIG_PQ2FADS
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-#endif
/* park bus on PCI */
immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
@@ -320,10 +286,6 @@ void __init pq2_find_bridges(void)
hose->bus_offset = 0;
hose->last_busno = 0xff;
-#ifdef CONFIG_ADS8272
- hose->set_cfg_type = 1;
-#endif
-
setup_m8260_indirect_pci(hose,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
(unsigned long)&cpm2_immr->im_pci.pci_cfg_data);