diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2005-09-06 06:59:47 +0200 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2005-09-06 08:57:46 +0200 |
| commit | 14b34661615ec036ab4c91637913706e4caccc93 (patch) | |
| tree | 98915b1889422383a85186d8455ecca69fa2327b /arch/ppc64/kernel | |
| parent | [PATCH] ppc64: Fix build with oprofile disabled (diff) | |
| download | linux-14b34661615ec036ab4c91637913706e4caccc93.tar.xz linux-14b34661615ec036ab4c91637913706e4caccc93.zip | |
[PATCH] Invert sense of SLB class bit
Currently, we set the class bit in kernel SLB entries, and clear it on
user SLB entries. On POWER5, ERAT entries created in real mode have
the class bit clear. So to avoid flushing kernel ERAT entries on each
context switch, this patch inverts our usage of the class bit, setting
it on user SLB entries and clearing it on kernel SLB entries.
Booted on POWER5 and G5.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/ppc64/kernel')
| -rw-r--r-- | arch/ppc64/kernel/entry.S | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/arch/ppc64/kernel/entry.S b/arch/ppc64/kernel/entry.S index b61572eb2a71..bf99b4a92f20 100644 --- a/arch/ppc64/kernel/entry.S +++ b/arch/ppc64/kernel/entry.S @@ -400,15 +400,14 @@ BEGIN_FTR_SECTION cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */ cror eq,4*cr1+eq,eq beq 2f /* if yes, don't slbie it */ - oris r0,r6,0x0800 /* set C (class) bit */ /* Bolt in the new stack SLB entry */ ld r7,KSP_VSID(r4) /* Get new stack's VSID */ - oris r6,r6,(SLB_ESID_V)@h - ori r6,r6,(SLB_NUM_BOLTED-1)@l - slbie r0 - slbie r0 /* Workaround POWER5 < DD2.1 issue */ - slbmte r7,r6 + oris r0,r6,(SLB_ESID_V)@h + ori r0,r0,(SLB_NUM_BOLTED-1)@l + slbie r6 + slbie r6 /* Workaround POWER5 < DD2.1 issue */ + slbmte r7,r0 isync 2: |