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authorConor Dooley <conor.dooley@microchip.com>2023-10-09 11:37:48 +0200
committerGeert Uytterhoeven <geert+renesas@glider.be>2023-11-13 14:35:36 +0100
commitbfc1d3a9011a35e673b026055194dc09e734742a (patch)
tree5ff1f7f56ebd1f05950c4686f756cca77580c7f5 /arch/riscv/boot
parentARM: dts: renesas: blanche: Add FLASH node (diff)
downloadlinux-bfc1d3a9011a35e673b026055194dc09e734742a.tar.xz
linux-bfc1d3a9011a35e673b026055194dc09e734742a.zip
riscv: dts: renesas: Convert isa detection to new properties
Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231009-smog-gag-3ba67e68126b@wendy Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/riscv/boot')
-rw-r--r--arch/riscv/boot/dts/renesas/r9a07g043f.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index b0796015e36b..a92cfcfc021b 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -24,6 +24,10 @@
reg = <0x0>;
status = "okay";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+ "zicntr", "zicsr", "zifencei",
+ "zihpm";
mmu-type = "riscv,sv39";
i-cache-size = <0x8000>;
i-cache-line-size = <0x40>;