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| author | Conor Dooley <conor.dooley@microchip.com> | 2023-10-24 10:20:35 +0200 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-11-16 22:43:52 +0100 |
| commit | e80ed63affc9a9b4aacb44180ecd7ed601839599 (patch) | |
| tree | 37069090145850568925115d1448c95ad985048a /arch/riscv/boot | |
| parent | Linux 6.7-rc1 (diff) | |
| download | linux-e80ed63affc9a9b4aacb44180ecd7ed601839599.tar.xz linux-e80ed63affc9a9b4aacb44180ecd7ed601839599.zip | |
riscv: dts: sophgo: remove address-cells from intc node
A recent submission [1] from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus, highlighting that
the new cv1800b DT has been incorrectly using #address-cells.
It has no child nodes, so #address-cells is not needed. Remove it.
Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..aec6401a467b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -34,7 +34,6 @@ cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; - #address-cells = <0>; #interrupt-cells = <1>; }; }; |