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| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-05-09 17:17:22 +0200 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-05-15 18:44:38 +0200 |
| commit | 435ac3fbfbc64a4557862a612058383748a3c7f0 (patch) | |
| tree | 144e58edfce076923084d36f9f0a0c339516c425 /arch/riscv/boot | |
| parent | riscv: dts: starfive: Add PMU controller node (diff) | |
| download | linux-435ac3fbfbc64a4557862a612058383748a3c7f0.tar.xz linux-435ac3fbfbc64a4557862a612058383748a3c7f0.zip | |
riscv: dts: starfive: jh7100: Add watchdog node
Add watchdog node for the StarFive JH7100 RISC-V SoC.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 000447482aca..4218621ea3b9 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -238,5 +238,15 @@ #size-cells = <0>; status = "disabled"; }; + + watchdog@12480000 { + compatible = "starfive,jh7100-wdt"; + reg = <0x0 0x12480000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_WDTIMER_APB>, + <&clkgen JH7100_CLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, + <&rstgen JH7100_RSTN_WDT>; + }; }; }; |