diff options
| author | Tong Tiangen <tongtiangen@huawei.com> | 2022-10-24 11:47:24 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-12-02 20:25:49 +0100 |
| commit | d33deda095d3637d218e7eed441633b2a01e1413 (patch) | |
| tree | 28491d2d24d33666d395360fd78426d176513906 /arch/riscv/include | |
| parent | RISC-V: defconfig: Enable CONFIG_SERIAL_8250_DW (diff) | |
| download | linux-d33deda095d3637d218e7eed441633b2a01e1413.tar.xz linux-d33deda095d3637d218e7eed441633b2a01e1413.zip | |
riscv/mm: hugepage's PG_dcache_clean flag is only set in head page
HugeTLB pages are always fully mapped, so only setting head page's
PG_dcache_clean flag is enough.
Signed-off-by: Tong Tiangen <tongtiangen@huawei.com>
Link: https://lore.kernel.org/lkml/20220331065640.5777-2-songmuchun@bytedance.com/
Link: https://lore.kernel.org/r/20221024094725.3054311-2-tongtiangen@huawei.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/cacheflush.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index 8a5c246b0a21..c172d05de474 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -17,6 +17,13 @@ static inline void local_flush_icache_all(void) static inline void flush_dcache_page(struct page *page) { + /* + * HugeTLB pages are always fully mapped and only head page will be + * set PG_dcache_clean (see comments in flush_icache_pte()). + */ + if (PageHuge(page)) + page = compound_head(page); + if (test_bit(PG_dcache_clean, &page->flags)) clear_bit(PG_dcache_clean, &page->flags); } |