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| author | Christoph Hellwig <hch@lst.de> | 2018-08-04 10:23:16 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-08-13 17:31:31 +0200 |
| commit | 6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde (patch) | |
| tree | dc077f5075634c43587aa2658247e37b4004e59d /arch/riscv/kernel/entry.S | |
| parent | RISC-V: add a definition for the SIE SEIE bit (diff) | |
| download | linux-6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde.tar.xz linux-6ea0f26a7913b2a72f9cbe84e77ad2cbeaaa9dde.zip | |
RISC-V: implement low-level interrupt handling
Add support for a routine that dispatches exceptions with the interrupt
flags set to either the IPI or irqdomain code (and the clock source in the
future).
Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/entry.S')
| -rw-r--r-- | arch/riscv/kernel/entry.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 9aaf6c986771..fa2c08e3c05e 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -168,8 +168,8 @@ ENTRY(handle_exception) /* Handle interrupts */ move a0, sp /* pt_regs */ - REG_L a1, handle_arch_irq - jr a1 + move a1, s4 /* scause */ + tail do_IRQ 1: /* Exceptions run with interrupts enabled */ csrs sstatus, SR_SIE |