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authorYash Shah <yash.shah@sifive.com>2020-01-03 05:13:20 +0100
committerPaul Walmsley <paul.walmsley@sifive.com>2020-01-03 09:56:23 +0100
commitcfda8617e22a8bf217a613d0b3ba3a38778443ba (patch)
tree85fbdb2001a712861d788616d17dc654e28740dd /arch/riscv/kernel/ftrace.c
parentriscv: gcov: enable gcov for RISC-V (diff)
downloadlinux-cfda8617e22a8bf217a613d0b3ba3a38778443ba.tar.xz
linux-cfda8617e22a8bf217a613d0b3ba3a38778443ba.zip
riscv: dts: Add DT support for SiFive L2 cache controller
Add the L2 cache controller DT node in SiFive FU540 soc-specific DT file Signed-off-by: Yash Shah <yash.shah@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
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