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| author | Sunil V L <sunilvl@ventanamicro.com> | 2023-05-15 07:49:16 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-06-01 17:45:03 +0200 |
| commit | f995611994704b5c039731287b897993808e63e3 (patch) | |
| tree | 40a204a525d1c8b289b6a189d8e0cb563718a8f4 /arch/riscv/kernel/setup.c | |
| parent | RISC-V: Add ACPI initialization in setup_arch() (diff) | |
| download | linux-f995611994704b5c039731287b897993808e63e3.tar.xz linux-f995611994704b5c039731287b897993808e63e3.zip | |
RISC-V: ACPI: Cache and retrieve the RINTC structure
RINTC structures in the MADT provide mapping between the hartid
and the CPU. This is required many times even at run time like
cpuinfo. So, instead of parsing the ACPI table every time, cache
the RINTC structures and provide a function to get the correct
RINTC structure for a given cpu.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20230515054928.2079268-10-sunilvl@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/kernel/setup.c')
| -rw-r--r-- | arch/riscv/kernel/setup.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 45df7cc88b19..2ab4cdaa2e68 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -22,6 +22,7 @@ #include <linux/efi.h> #include <linux/crash_dump.h> +#include <asm/acpi.h> #include <asm/alternative.h> #include <asm/cacheflush.h> #include <asm/cpu_ops.h> @@ -298,6 +299,9 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif + if (!acpi_disabled) + acpi_init_rintc_map(); + riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); apply_boot_alternatives(); |