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| author | Christoph Hellwig <hch@lst.de> | 2023-10-28 17:51:01 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-11-07 18:37:42 +0100 |
| commit | 946bb33d330251966223f770f64885c79448b1a1 (patch) | |
| tree | 67ac511133dd5b26ed1a8f2a03f77db42b6ca3ab /arch/riscv/mm/Makefile | |
| parent | Merge patch series "riscv: tlb flush improvements" (diff) | |
| download | linux-946bb33d330251966223f770f64885c79448b1a1.tar.xz linux-946bb33d330251966223f770f64885c79448b1a1.zip | |
riscv: split cache ops out of dma-noncoherent.c
The cache ops are also used by the pmem code which is unconditionally
built into the kernel. Move them into a separate file that is built
based on the correct config option.
Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> #
Link: https://lore.kernel.org/r/20231028155101.1039049-1-hch@lst.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm/Makefile')
| -rw-r--r-- | arch/riscv/mm/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index 9c454f90fd3d..3a4dfc8babcf 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -36,3 +36,4 @@ endif obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) += dma-noncoherent.o +obj-$(CONFIG_RISCV_NONSTANDARD_CACHE_OPS) += cache-ops.o |