diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2023-03-28 05:52:22 +0200 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2023-04-08 12:26:24 +0200 |
| commit | 6279228432352f43f43f5e760771151605bf6d82 (patch) | |
| tree | e8a3aef57fad6c5c9a98419754e1d300a183c3de /arch/riscv/mm/cacheflush.c | |
| parent | RISC-V: Use IPIs for remote TLB flush when possible (diff) | |
| download | linux-6279228432352f43f43f5e760771151605bf6d82.tar.xz linux-6279228432352f43f43f5e760771151605bf6d82.zip | |
RISC-V: Use IPIs for remote icache flush when possible
If we have specialized interrupt controller (such as AIA IMSIC) which
allows supervisor mode to directly inject IPIs without any assistance
from M-mode or HS-mode then using such specialized interrupt controller,
we can do remote icache flushe directly from supervisor mode instead of
using the SBI RFENCE calls.
This patch extends remote icache flush functions to use supervisor mode
IPIs whenever direct supervisor mode IPIs.are supported by interrupt
controller.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230328035223.1480939-7-apatel@ventanamicro.com
Diffstat (limited to 'arch/riscv/mm/cacheflush.c')
| -rw-r--r-- | arch/riscv/mm/cacheflush.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index fcd6145fbead..20cec5e7cdbf 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -19,7 +19,7 @@ void flush_icache_all(void) { local_flush_icache_all(); - if (IS_ENABLED(CONFIG_RISCV_SBI)) + if (IS_ENABLED(CONFIG_RISCV_SBI) && !riscv_use_ipi_for_rfence()) sbi_remote_fence_i(NULL); else on_each_cpu(ipi_remote_fence_i, NULL, 1); @@ -67,7 +67,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local) * with flush_icache_deferred(). */ smp_mb(); - } else if (IS_ENABLED(CONFIG_RISCV_SBI)) { + } else if (IS_ENABLED(CONFIG_RISCV_SBI) && + !riscv_use_ipi_for_rfence()) { sbi_remote_fence_i(&others); } else { on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1); |