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| author | Yangyu Chen <cyy@cyyself.name> | 2024-02-21 04:02:31 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-22 21:21:27 +0100 |
| commit | c21f014818600ae017f97ee087e7c136b1916aa7 (patch) | |
| tree | 14cf1ce4d9d5d406c1456a8cf2f722435491b2ed /arch/riscv/mm | |
| parent | riscv: add CALLER_ADDRx support (diff) | |
| download | linux-c21f014818600ae017f97ee087e7c136b1916aa7.tar.xz linux-c21f014818600ae017f97ee087e7c136b1916aa7.zip | |
riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
Previous commit dbfbda3bd6bf ("riscv: mm: update T-Head memory type
definitions") from patch [1] missed a `<` for bit shifting, result in
bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
This patch get this fixed.
Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
Fixes: dbfbda3bd6bf ("riscv: mm: update T-Head memory type definitions")
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/tencent_E19FA1A095768063102E654C6FC858A32F06@qq.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm')
0 files changed, 0 insertions, 0 deletions