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| author | Paul Walmsley <paul.walmsley@sifive.com> | 2019-10-11 00:57:58 +0200 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-10-14 21:35:36 +0200 |
| commit | 4c8eb19cf9dc5fcc489757acbf93be90baf25848 (patch) | |
| tree | e0c65f24364f91e5e363e6ac3b568871041711cc /arch/riscv | |
| parent | riscv: dts: HiFive Unleashed: add default chosen/stdout-path (diff) | |
| download | linux-4c8eb19cf9dc5fcc489757acbf93be90baf25848.tar.xz linux-4c8eb19cf9dc5fcc489757acbf93be90baf25848.zip | |
riscv: tlbflush: remove confusing comment on local_flush_tlb_all()
Remove a confusing comment on our local_flush_tlb_all()
implementation. Per an internal discussion with Andrew, while it's
true that the fence.i is not necessary, it's not the case that an
sfence.vma implies a fence.i. We also drop the section about
"flush[ing] the entire local TLB" to better align with the language in
section 4.2.1 "Supervisor Memory-Management Fence Instruction" of the
RISC-V Privileged Specification v20190608.
Fixes: c901e45a999a1 ("RISC-V: `sfence.vma` orderes the instruction cache")
Reported-by: Alan Kao <alankao@andestech.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/tlbflush.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h index 37ae4e367ad2..f02188a5b0f4 100644 --- a/arch/riscv/include/asm/tlbflush.h +++ b/arch/riscv/include/asm/tlbflush.h @@ -10,10 +10,6 @@ #include <linux/mm_types.h> #include <asm/smp.h> -/* - * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction - * cache as well, so a 'fence.i' is not necessary. - */ static inline void local_flush_tlb_all(void) { __asm__ __volatile__ ("sfence.vma" : : : "memory"); |