diff options
| author | Minda Chen <minda.chen@starfivetech.com> | 2023-07-26 12:06:09 +0200 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-07-26 18:13:37 +0200 |
| commit | e126aa3abc4e2388f0e1b367f47b0a24780daa4e (patch) | |
| tree | a4a5220dd36b0854df29ff9cad0ef13a911d69f3 /arch/riscv | |
| parent | riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110 (diff) | |
| download | linux-e126aa3abc4e2388f0e1b367f47b0a24780daa4e.tar.xz linux-e126aa3abc4e2388f0e1b367f47b0a24780daa4e.zip | |
riscv: dts: starfive: Add USB dts node for JH7110
Add USB wrapper layer and Cadence USB3 controller dts
configuration for StarFive JH7110 SoC and VisionFive2
Board.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 5 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 32 |
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 5feff4673503..36c402b4a726 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -273,6 +273,11 @@ status = "okay"; }; +&usb0 { + dr_mode = "peripheral"; + status = "okay"; +}; + &U74_1 { cpu-supply = <&vdd_cpu>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index dbc1243a0e75..c58489468cad 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -446,6 +446,38 @@ status = "disabled"; }; + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + usbphy0: phy@10200000 { compatible = "starfive,jh7110-usb-phy"; reg = <0x0 0x10200000 0x0 0x10000>; |