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| author | Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 23:02:50 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-28 23:03:29 +0100 |
| commit | 8286d51a6c244738aeb071fcd7d2e36a3374e150 (patch) | |
| tree | 6c54619aa865b731d9682c39cc27e40d65090fd0 /arch/riscv | |
| parent | RISC-V: Remove unused arguments from ATOMIC_OP (diff) | |
| download | linux-8286d51a6c244738aeb071fcd7d2e36a3374e150.tar.xz linux-8286d51a6c244738aeb071fcd7d2e36a3374e150.zip | |
RISC-V: Comment on why {,cmp}xchg is ordered how it is
This is another memory model FIXME.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/atomic.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index 40c73dd59c15..e65d1cd89e28 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -300,8 +300,13 @@ static __always_inline long atomic64_inc_not_zero(atomic64_t *v) /* * atomic_{cmp,}xchg is required to have exactly the same ordering semantics as - * {cmp,}xchg and the operations that return, so they need a barrier. We just - * use the other implementations directly. + * {cmp,}xchg and the operations that return, so they need a barrier. + */ +/* + * FIXME: atomic_cmpxchg_{acquire,release,relaxed} are all implemented by + * assigning the same barrier to both the LR and SC operations, but that might + * not make any sense. We're waiting on a memory model specification to + * determine exactly what the right thing to do is here. */ #define ATOMIC_OP(c_t, prefix, c_or, size, asm_or) \ static __always_inline c_t atomic##prefix##_cmpxchg##c_or(atomic##prefix##_t *v, c_t o, c_t n) \ |