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authorJan Glauber <jang@linux.vnet.ibm.com>2012-11-29 13:05:05 +0100
committerMartin Schwidefsky <schwidefsky@de.ibm.com>2012-11-30 17:47:21 +0100
commit9a4da8a5b109906a64bed5aaeb83bf4edb1f5888 (patch)
tree2788d7c8fe3e90333555435c7539d9f31d2c520e /arch/s390/kernel/irq.c
parents390/bitops: find leftmost bit instruction support (diff)
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s390/pci: PCI adapter interrupts for MSI/MSI-X
Support PCI adapter interrupts using the Single-IRQ-mode. Single-IRQ-mode disables an adapter IRQ automatically after delivering it until the SIC instruction enables it again. This is used to reduce the number of IRQs for streaming workloads. Up to 64 MSI handlers can be registered per PCI function. A hash table is used to map interrupt numbers to MSI descriptors. The interrupt vector is scanned using the flogr instruction. Only MSI/MSI-X interrupts are supported, no legacy INTs. Signed-off-by: Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/kernel/irq.c')
-rw-r--r--arch/s390/kernel/irq.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index 6cdc55b26d68..bf24293970ce 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -58,6 +58,8 @@ static const struct irq_class intrclass_names[] = {
[IOINT_APB] = {.name = "APB", .desc = "[I/O] AP Bus"},
[IOINT_ADM] = {.name = "ADM", .desc = "[I/O] EADM Subchannel"},
[IOINT_CSC] = {.name = "CSC", .desc = "[I/O] CHSC Subchannel"},
+ [IOINT_PCI] = {.name = "PCI", .desc = "[I/O] PCI Interrupt" },
+ [IOINT_MSI] = {.name = "MSI", .desc = "[I/O] MSI Interrupt" },
[NMI_NMI] = {.name = "NMI", .desc = "[NMI] Machine Check"},
};