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authorIngo Molnar <mingo@elte.hu>2010-12-08 20:15:26 +0100
committerIngo Molnar <mingo@elte.hu>2010-12-08 20:15:29 +0100
commit8e9255e6a2141e050d51bc4d96dbef494a87d653 (patch)
treef190b142830153eaab05555a93c4f71a144ba3d4 /arch/sh/boards/mach-ecovec24/setup.c
parentsched: Add 'autogroup' scheduling feature: automated per session task groups (diff)
parentMerge branches 'x86-fixes-for-linus', 'perf-fixes-for-linus' and 'sched-fixes... (diff)
downloadlinux-8e9255e6a2141e050d51bc4d96dbef494a87d653.tar.xz
linux-8e9255e6a2141e050d51bc4d96dbef494a87d653.zip
Merge branch 'linus' into sched/core
Merge reason: we want to queue up dependent cleanup Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/sh/boards/mach-ecovec24/setup.c')
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c34
1 files changed, 4 insertions, 30 deletions
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 2eaeb9e59585..f48c492a68d3 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -720,32 +720,6 @@ static struct platform_device camera_devices[] = {
};
/* FSI */
-/*
- * FSI-B use external clock which came from da7210.
- * So, we should change parent of fsi
- */
-#define FCLKBCR 0xa415000c
-static void fsimck_init(struct clk *clk)
-{
- u32 status = __raw_readl(clk->enable_reg);
-
- /* use external clock */
- status &= ~0x000000ff;
- status |= 0x00000080;
-
- __raw_writel(status, clk->enable_reg);
-}
-
-static struct clk_ops fsimck_clk_ops = {
- .init = fsimck_init,
-};
-
-static struct clk fsimckb_clk = {
- .ops = &fsimck_clk_ops,
- .enable_reg = (void __iomem *)FCLKBCR,
- .rate = 0, /* unknown */
-};
-
static struct sh_fsi_platform_info fsi_info = {
.portb_flags = SH_FSI_BRS_INV |
SH_FSI_OUT_SLAVE_MODE |
@@ -1264,10 +1238,10 @@ static int __init arch_setup(void)
/* change parent of FSI B */
clk = clk_get(NULL, "fsib_clk");
if (!IS_ERR(clk)) {
- clk_register(&fsimckb_clk);
- clk_set_parent(clk, &fsimckb_clk);
- clk_set_rate(clk, 11000);
- clk_set_rate(&fsimckb_clk, 11000);
+ /* 48kHz dummy clock was used to make sure 1/1 divide */
+ clk_set_rate(&sh7724_fsimckb_clk, 48000);
+ clk_set_parent(clk, &sh7724_fsimckb_clk);
+ clk_set_rate(clk, 48000);
clk_put(clk);
}