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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 09:43:28 +0200
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 09:43:28 +0200
commit959f85f8a3223c116bbe95dd8a9b207790b5d4d3 (patch)
treee7da9ccf292f860bfa0ff9cc8b2682cd1d6bad4d /arch/sh/drivers/pci/fixups-rts7751r2d.c
parentserial: Rework sh-sci for driver model. (diff)
downloadlinux-959f85f8a3223c116bbe95dd8a9b207790b5d4d3.tar.xz
linux-959f85f8a3223c116bbe95dd8a9b207790b5d4d3.zip
sh: Consolidated SH7751/SH7780 PCI support.
This cleans up quite a lot of the PCI mess that we currently have, and attempts to consolidate the duplication in the SH7780 and SH7751 PCI controllers. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/fixups-rts7751r2d.c')
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 0c590fc7a081..e72ceb560d5b 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -10,8 +10,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-#include "pci-sh7751.h"
-#include <asm/io.h>
+#include "pci-sh4.h"
#define PCIMCR_MRSET_OFF 0xBFFFFFFF
#define PCIMCR_RFSH_OFF 0xFFFFFFFB
@@ -22,22 +21,23 @@ int pci_fixup_pcic(void)
bcr1 = inl(SH7751_BCR1);
bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
- outl(bcr1, PCI_REG(SH7751_PCIBCR1));
+ pci_write_reg(bcr1, SH4_PCIBCR1);
/* Enable all interrupts, so we known what to fix */
- outl(0x0000c3ff, PCI_REG(SH7751_PCIINTM));
- outl(0x0000380f, PCI_REG(SH7751_PCIAINTM));
+ pci_write_reg(0x0000c3ff, SH4_PCIINTM);
+ pci_write_reg(0x0000380f, SH4_PCIAINTM);
- outl(0xfb900047, PCI_REG(SH7751_PCICONF1));
- outl(0xab000001, PCI_REG(SH7751_PCICONF4));
+ pci_write_reg(0xfb900047, SH7751_PCICONF1);
+ pci_write_reg(0xab000001, SH7751_PCICONF4);
mcr = inl(SH7751_MCR);
mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
- outl(mcr, PCI_REG(SH7751_PCIMCR));
+ pci_write_reg(mcr, SH4_PCIMCR);
+
+ pci_write_reg(0x0c000000, SH7751_PCICONF5);
+ pci_write_reg(0xd0000000, SH7751_PCICONF6);
+ pci_write_reg(0x0c000000, SH4_PCILAR0);
+ pci_write_reg(0x00000000, SH4_PCILAR1);
- outl(0x0c000000, PCI_REG(SH7751_PCICONF5));
- outl(0xd0000000, PCI_REG(SH7751_PCICONF6));
- outl(0x0c000000, PCI_REG(SH7751_PCILAR0));
- outl(0x00000000, PCI_REG(SH7751_PCILAR1));
return 0;
}