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| author | Paul Mundt <lethal@linux-sh.org> | 2007-11-22 08:29:10 +0100 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 05:18:55 +0100 |
| commit | b6d7b666097e79a8908e3c43fd55fd291a95e133 (patch) | |
| tree | 61ab633feecd144d129fc3b220ecb9376c7949bd /arch/sh/drivers/pci/pci-sh5.h | |
| parent | sh: Bump number of quicklists for SH-5. (diff) | |
| download | linux-b6d7b666097e79a8908e3c43fd55fd291a95e133.tar.xz linux-b6d7b666097e79a8908e3c43fd55fd291a95e133.zip | |
sh: Get the SH-5 PCI support building.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/pci-sh5.h')
| -rw-r--r-- | arch/sh/drivers/pci/pci-sh5.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h index c71159dd04b9..7cff3fc04d30 100644 --- a/arch/sh/drivers/pci/pci-sh5.h +++ b/arch/sh/drivers/pci/pci-sh5.h @@ -6,6 +6,8 @@ * * Definitions for the SH5 PCI hardware. */ +#ifndef __PCI_SH5_H +#define __PCI_SH5_H /* Product ID */ #define PCISH5_PID 0x350d @@ -73,13 +75,12 @@ #define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */ #define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */ - - /* Base address of registers */ #define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000) #define SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000) /* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG) */ +extern unsigned long pcicr_virt; /* Register selection macro */ #define PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x)) /* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */ @@ -104,4 +105,9 @@ #define PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18) #define PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18) +extern struct pci_ops sh5_pci_ops; + +/* arch/sh/drivers/pci/pci-sh5.c */ +int sh5pci_init(unsigned long memStart, unsigned long memSize); +#endif /* __PCI_SH5_H */ |