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author | David Howells <dhowells@redhat.com> | 2012-10-09 10:47:37 +0200 |
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committer | David Howells <dhowells@redhat.com> | 2012-10-09 10:47:37 +0200 |
commit | 0a9426df1858f71ac84eb7eef500b4247de5e3bb (patch) | |
tree | 82983766b53c18f5da8602f16ed0b67ae2a957fb /arch/sh/include/uapi/asm/auxvec.h | |
parent | Merge branch 'akpm' (Andrew's patch-bomb) (diff) | |
download | linux-0a9426df1858f71ac84eb7eef500b4247de5e3bb.tar.xz linux-0a9426df1858f71ac84eb7eef500b4247de5e3bb.zip |
UAPI: (Scripted) Disintegrate arch/sh/include/asm
Signed-off-by: David Howells <dhowells@redhat.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Michael Kerrisk <mtk.manpages@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'arch/sh/include/uapi/asm/auxvec.h')
-rw-r--r-- | arch/sh/include/uapi/asm/auxvec.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/sh/include/uapi/asm/auxvec.h b/arch/sh/include/uapi/asm/auxvec.h new file mode 100644 index 000000000000..8bcc51af9367 --- /dev/null +++ b/arch/sh/include/uapi/asm/auxvec.h @@ -0,0 +1,38 @@ +#ifndef __ASM_SH_AUXVEC_H +#define __ASM_SH_AUXVEC_H + +/* + * Architecture-neutral AT_ values in 0-17, leave some room + * for more of them. + */ + +/* + * This entry gives some information about the FPU initialization + * performed by the kernel. + */ +#define AT_FPUCW 18 /* Used FPU control word. */ + +#if defined(CONFIG_VSYSCALL) || !defined(__KERNEL__) +/* + * Only define this in the vsyscall case, the entry point to + * the vsyscall page gets placed here. The kernel will attempt + * to build a gate VMA we don't care about otherwise.. + */ +#define AT_SYSINFO_EHDR 33 +#endif + +/* + * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + * value is -1, then the cache doesn't exist. Otherwise: + * + * bit 0-3: Cache set-associativity; 0 means fully associative. + * bit 4-7: Log2 of cacheline size. + * bit 8-31: Size of the entire cache >> 8. + */ +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 + +#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */ + +#endif /* __ASM_SH_AUXVEC_H */ |